This invention relates to a semiconductor memory device comprising ferroelectric capacitors.
With the development of computers, semiconductor memory devices are becoming popular for storing data and programs. Examples of semiconductor memory device include RAM (random access memory) devices such as DRAM and SRAM and ROM (read only memory) devices such as mask ROM and PROM. ROMs are usually non-volatile such that the data-storing condition is maintained even if the device is disconnected from a power source. PROM (programmable read only memory) devices are becoming particularly popular because the use can freely write in data. EEPROM (electrically erasable PROM) devices are particularly expected to become-popular because data can be written in electrically.
One of known methods of producing an EEPROM has been to make use of the MIS-FET (metal-insulator-semiconductor field effect transistor) structure, maintaining a data-storing condition by charge injection from a silicon substrate or charge discharge to the substrate by using a trap region inside the gate insulator membrane or a floating gate. Another method has been to apply a high voltage to a ferroelectric membrane to cause spontaneous polarization. Examples of the method of using a ferroelectric member include the method of causing spontaneous polarization of a ferroelectric member serving as a gate insulator membrane by applying a high gate voltage by using its MFS-FET (metal-ferroelectric-semiconductor FET) structure, as well as the method of using a ferroelectric material instead of an oxide membrane as capacitor in a DRAM-like circuit structure. The latter method, in particular, is being actively developed recently because it is possible to provide non-volatility while taking advantage of the merit that the cell structure is simple, being similar to a DRAM.
As an example of semiconductor memory device with a DRAM-like circuit structure and using ferroelectric capacitors, Japanese Patent Publication Tokkai 8-36888 disclosed a circuit structure as shown in FIG. 8, wherein WL0-WL3 are word lines, DWL0-DWL1 are dummy word lines, BL0, /BL0, BL1 and /BL1 are bit lines, CP0 and CP1 are plate lines, DCP0 and DCPL are dummy plate lines, EQ11 indicates a bit equalize and precharge control signal, S100 and S101 indicate control signals, V10 indicates a signal, SAE0 and SAE1 indicate sense amplifier control signals, V.sub.ss indicates a grounding voltage, SA0 and SA1 are sense amplifiers, Cs1-Cs8 are main body memory cell ferroelectric capacitors, Cd1-Cd4 are dummy memory cell ferroelectric capacitors, Cb1-Cb4 are bit line capacitance adjusting capacitors each comprising an ordinary capacitor or a ferroelectric capacitor, and Qn is an N-channel type MOS transistor.
In order to read out data with a circuit structure as described above, the word lines WL0-WL3, the dummy word lines DWL0 and DWL1, the plate lines CPO and CP1, the dummy plate lines DCP0 and DCP1, the sense amplifier control signals SAE0 and SAE1 and the control signals S100 and S101 are set to logical voltage "L", the bit equalize and precharge control signal EQ11 is set to logical voltage "H" and the bit lines BL0, /BL0, BL1 and /BL1 are set to logical voltage "L" as initial condition. Next, the signal EQ11 is set to "L" such that the bit lines BL0, /BL0, BL1 and /BL1 are in a floating condition. If it is desired now to read the main body memory cell capacitor Cs2, word line WL1, dummy word line DWL1, plate line CP0, dummy plate line DCP0 and control signal S101 are all set to "H" such that the MOS transistor Qn is activated and the data signal from the dummy memory cell is outputted to the bit line BL0 and the data signal from the main body memory cell is outputted to the bit line /BL0. In this situation, the control signal S101 becomes "H" such that the bit line BL0 becomes connected to the bit line capacitance adjusting capacitors but the circuit is so set that a suitable reference voltage can be obtained by setting the signal V10 at an appropriate voltage to increase the capacitance of the bit line BL0 even if the dummy memory cell capacitor and the main body memory cell capacitor are about the same. If the sense amplifier control signal SAEO is thereafter set to "H" to activate the sense amplifier SA0, the data on the bit lines BL0 and/BL0 are compared and amplified and the memory stored in the capacitor Cs2 is outputted.
As explained above, ferroelectric capacitors function as a non-volatile memory device by making use of residual spontaneous polarization of a ferroelectric material. FIG. 9 shows the hysteresis characteristic of a ferroelectric material, the horizontal axis representing the voltage which is applied to the material and the vertical axis representing the charge as an equivalent of its polarization condition. The solid curve represents the characteristic when no pressure is applied to the ferroelectric material, and the dotted curve represents the characteristic when the material is subjected to a pressure.
As shown by Points B and D on the solid curve of FIG. 9, a ferroelectric material has residual polarization even when the applied voltage is "0". If a sufficiently large positive voltage is applied when the material is at Point "D", its condition changed to Point "A". If the applied voltage is thereafter reduced to "0", the condition of the material does not return to Point "D" but moves to Point "B". If a positive voltage is applied again under this condition, the polarization condition of the material changes only from Point "B" to Point "A", but if a sufficiently large negative voltage is applied first and then the voltage is returned to "0", the polarization condition goes back to Point "D". Such a material can be used as a memory device by corresponding the polarization conditions of Points "B" and "D" with logical values "1" and "0".
Ferroelectric materials, however, also have a piezoelectric characteristic, causing voltage variations when subjected to external pressure. As shown in FIG. 9, for example, the hysteresis characteristic of the ferroelectric material may change from the curve shown by solid lines to the truncated curve shown by dotted lines. The accumulated charge may increase at Points "A" and "C" to Points "A'" and "C'" but Points "B" and "D" corresponding to a zero-voltage situation may move to Points "B'" and "D'" as shown, the accumulated charge becoming smaller.
Let us now consider the shift in the read-out voltage. If C.sub.p represents the load capacitance in FIG. 9, the read-out voltages are graphically obtained as V.sub.1 and V.sub.2 when there is no external pressure. In other words, this material can function as a memory device by setting the reference voltage V.sub.ref between V.sub.1 and V.sub.2 as shown in FIG. 9, V.sub.1 and V.sub.2 corresponding to logical values "1" and "0". When the ferroelectric material is under pressure, however, voltages V.sub.1 ' and V.sub.2 ' are similarly obtained from FIG. 9, but since V.sub.1 ' is smaller than V.sub.ref, it is likely to be interpreted as logical value "0".
FIGS. 10A and 10B show schematically the voltage shifts due to piezoelectric properties of ferroelectric material caused when external pressure is applied to a semiconductor memory device, the horizontal axes representing the positions of detection and the vertical axes representing the detection voltage. As shown, the detection voltage changes according to the applied distortion pressure at each detection position.
Consider FIG. 10A, for example. When the dummy memory cell capacitors and the bit line capacitance adjusting capacitors in the circuit of FIG. 8 are in a condition indicated by Point "A" of FIG. 9, the voltage difference between the reference voltage generated from these capacitors and the detection voltage V.sub.A is used for the memory read-out. If there is a memory cell in a condition of Point "C", there is no problem in comparing with the reference voltage because the detection voltage is V.sub.A, being the same as Point "A". In the case of a memory cell in a condition of Point "B", however, there is an error of (V.sub.A -V.sub.B) to be taken into consideration when a comparison is made with the reference voltage because the detection voltage is V.sub.B.
Consider FIG. 10B next. When the dummy memory cell capacitors and the bit line capacitance adjusting capacitors in the circuit of FIG. 8 are in a condition indicated by Point "A" of FIG. 9, there is no problem with a memory cell at Position "D", but a maximum error of (V.sub.A -V.sub.C) should be expected for memory cells in other conditions.
In summary, the read-out margin of a ferroelectric is lowered due to an external force, as shown in FIG. 9, and when an external force is applied unevenly on a packaged semiconductor memory device, shear pressure is applied locally thereon and different voltage differences will be experienced, depending on the distribution of the memory cells, as shown in FIGS. 10A and 10B. In particular when a pressure is locally applied on ferroelectric capacitors which are located only in one limited region such as the dummy memory cell capacitors and the bit line capacitance adjusting capacitors in the semiconductor memory device of FIG. 8, the read-out margin is reduced and, in worse situations, errors can occur in the read-out of data. In general, the read-out of information from a ferroelectric memory device is by destroying the stored data item and a data-rewrite is required after the data item has been read. Thus, if the data item stored in a ferroelectric memory device is incorrectly read out, an incorrect data item will be received thereafter and stored in the memory device.